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Key in, TX Delay and CW Delay (holdoff)
I there a timing diagram that shows the relationship between the key down, TX Delay and the CW PTT return to RX. Using an 8600 and PGXL. The manual is not clear and a diagram would be great.
I'm not clear about when the RF is actually output to the antenna.
Is the start of the CW signal delayed by the TX Delay?
- At 30 WPM a dit is 40ms. If I set the TX Delay to 30ms, does the RF output begin at 30ms with the complete 40ms dit?
2. If the CW delay is 15ms (PTT returns to RX) does the dit complete or is it truncated?
Thanks.
Answers
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There is a timing chart, but I can't put my hands on it at the moment.
Let me if I can explain this accurately.
TX Delay is added on to the end of the Longest of TX1, 2 or 3 delay.
Yes, the CW is delayed and buffered by the addition of those 2 times. The return to RX is after the completion of the CW elements so not truncated.
You can test this by setting up a 1000ms delay and listening / seeing what happens (as a test).
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Hi Mike,
Lets say I have only the TX delay set.
The RF output starts at the end of the TX delay and ends at the sum of the TX delay and the CW delay. Is that correct?
The CW delay is triggered on the rising edge of the key input but it is not applied until after the TX delay period. Is that correct?
So, using the numbers in my original post, the TX delay plus the CW delay (30ms + 15ms = 45ms), when PTT returns to RX, should allow the dit to be completed.
The radio will unassert PTT between characters for this scenario,
Does that make sense?
I believe that at sometime in the past I connected a scope to the key input, a sample of the RF output, and the PTT but I couldn't find my notes with the result. Thus my question.I may have to try again.
Thanks.
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1
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OK, the timing diagram is mostly complete.
At the top right of the diagram is a block labeled "FIFO Buffer Empty" which starts the RF ramp-down.
The CW holdoff delay is not shown in the diagram.
What I'm trying to understand is the relationship between the FIFO Buffer Empty state and the CW holdoff delay. Is the CW delay implemented after the FIFO buffer is empty? If not where?
Thanks.
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I have asked someone to respond from engineering.
Is there a problem you are having here?
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That is a good question, Geoff. One that will take a bit of investigation to answer. Watch this space - it may take a day or two.
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Thanks Mike and Dan…Standing By.
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Hi Mike and/or Dan,
Do you have any info regarding my question?
Thanks!
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