Some questions about the 6700's sampling specs?

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I have been reviewing my Flex 6700's published specs. SDRs use I & Q data for all its calculations, and the 6700 has an ADC that performs 245 million samples per second, each one 64 bits deep.

I assume each sample holds 32 bits of I data and another 32 bits of Q data...

Is that correct?


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Roy Laufer

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Posted 3 years ago

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Alan Davis

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Hi Roy,

The ADC sampling is 16 bits wide at 245.76Ms/s. That torrent of data, representing all activity from 30KHz to 77MHz is passed to the FPGA, where it is decimated (certain samples tossed out) and converted into different IQ data streams, one of which is at 24Ks/s. A Slice receiver's DSP processing takes care of bandwidth control, demodulation, ANF, NR, AGC etc. and eventually produces audio. The numeric precision used in DSP processing is much higher than 16 bits, perhaps 64 bit floating point, but I'm not certain. If math precision is high enough then errors due to lack of precision stay below the noise floor of the panadaptor and slice Rx and won't be seen or heard by the user. Did that help somewhat?

73, K2WS
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Steve - N5AC, VP Engineering / CTO

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The ADC is 16 bits as Alan notes.  245.76MHz is substantially oversampled from the final receiver bandwidth and so significant gain is achieved through decimation (see  As you decimate, the bandwidth and data rate are reduced and bit-depth is increased.  The eventual output is IQ data at 32-bits each, but all bits are not populated since decimation doesn't achieve 32-bits of data.  It's closer to two 24-bit numbers.
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Steve - N5AC, VP Engineering / CTO

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Roy, I forwarded you a lengthy email I sent to Bob Fuller, W7KWS, with some background I think may help you and your friend -- his questions were along the same lines.  Take a read and let me know if there's other questions you have.  It's pretty long and technical as well as very open about some details and I probably wouldn't post it here anyway -- it's written more as a personal note.
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KY6LA - Howard, Elmer

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Please post it here.. some of us technonerds love to read this stuff
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I would make an interesting read 4 sure.
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Steve - N5AC, VP Engineering / CTO

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Howard & Tim, I'll try to clean it up and post something in the next few weeks.  I'm totally buried working on Maestro and should spend my time on it.
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Winston VK7WH

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Steve, I think all of us appreciate the pressures you must be working under, pre the Maestro release Steve, and I'm sure we can wait to see the edited document when you have more time.