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What are the electrical characteristics of the interlock inputs?
Bob N7ZO
Member ✭✭
I cannot find any description of the electrical characteristics of the interlock inputs other than "3.3VDC Max. Input" and the software selection of Active High or Active Low. What kind of signal do I need to provide to these?
Also, what is the timing relationship between the interlock inputs and the TX 1,2,3 outputs and "TX Delay"? Does the "TX Delay" occur after the interlock has been released?
73, Bob, N7ZO
Also, what is the timing relationship between the interlock inputs and the TX 1,2,3 outputs and "TX Delay"? Does the "TX Delay" occur after the interlock has been released?
73, Bob, N7ZO
1
Answers
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Still no reply? I'd like to know this, myself. Two years ago it was said the xmit interlock was not yet active. See reply to Bob G, W1GLV. Is this still true with the latest release? 73, Jim0
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I believe this is the diagram that we coded to for the outputs. Someone else will need to speak up about the electrical characteristics.

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This can be controlled with a 3.3V to 5V logic signal. The circuit is a 74LVC14 CMOS Schmidt trigger logic input with a 2.7k pullup to +3.3V. The IC is 5V tolerant so you can drive it with TTL levels as well. It can also be driven with an open collector transistor or open drain MOSFET.0
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Gerald, your hardware description is precise. Maybe this could be included in the manual.
Eric, your graphic matches the text in the hardware manual, but does not discuss the interlock input timing. Specifically, do the TX delays start after the interlock has been released or do the delays occur and then the final transmit keying occurs as soon as the inhibit is released?
Thank you both, Bob, N7ZO
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Gerald, your hardware description is precise. Maybe this could be included in the manual.
It is already included in the next version of the hardware manual.1 -
Are we talking about the TX Request line (input) or the TX 1/2/3 lines (outputs)? The TX 1/2/3 outputs switch AFTER the delay going from RX->TX. I believe they do just the opposite TX->RX, but I would need to verify that in the source.
The TX Request line is a different animal. It is a holdoff until the hardware says that it is OK to transmit. The question is what does it hold off? I don't know this answer off-hand, and would again have to study the source. I'm happy to do this if this is what is being asked. If not, please clarify.
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Hi Eric,
Yes, I am asking about the TX Request input which is also referred to as an interlock input in both the hardware and software manuals.
The TX outputs are well documented.
73, Bob, N7ZO
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It is my understanding that the TX Request line is yet another gate that would need to be cleared before the radio would actually emit RF. It would not cause the TX 1/2/3 lines not to toggle. If the TX Request line switches prior to getting to the "emit RF" part of the attached graphic, there would be no change in the timing. If it hasn't flipped by that time, the emit RF portion would be pushed out until the TX Request switches or a timeout is met.0
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That describes it well.
Thank you, Bob, N7ZO
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