It is my understanding that there is a frequency error inherent in synthesized radios due to the use of an algorithm or lookup-table to generate a particular frequency.

If I add that error to the GPS error, I should have a good idea of the total error. How do I find out the error that is part of the synthesis system?

If I add that error to the GPS error, I should have a good idea of the total error. How do I find out the error that is part of the synthesis system?

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Posted 4 years ago

Steve - N5AC, VP Engineering

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Official Response

Generally speaking, there are several ways to create an oscillator on a given frequency. Two of the most popular are phase locking (PLL) and direct synthesis. Phase locking yields a frequency on-channel, but the phase noise of the oscillator can exceed the requirements of some applications (including sometimes HF radio). The phase noise in a PLL is a factor of the tuning range (the larger window you can tune, the more phase noise you will likely have).

I've not watched this, but Analog devices has a webcast to explain the fundamentals of PLLs: http://www.analog.com/en/content/WC_FUN_PLL/webcast.html

In direct digital synthesis (DDS), the frequency is created by actually creating a sine wave over time. Small increments of phase angle are added to an accumulator over time and then the accumulator is examined to create a voltage proportional to the current position of the sine wave. DSS ICs can be purchased and programmed with a microprocessor to perform this function.

I've not watched this one either, but it's from Analog so it's probably very good: Webcast explaining the fundamentals of DDSs:

http://www.analog.com/en/content/WC_FUN_DDS/webcast.html

To create the frequency output, a DDS has a reference clock that serves as its time base. The tuned frequency is loaded into a tuning word. The generalized formula for a DDS to determine the output frequency is:

(1)

(* is a multiply operation, / is a divide operation)

For a 245.76MHz clock (the clock in the FLEX-6700) and a 32-bit tuning word, we get:

(2^32 is 2 to the 32nd power or 4,294,967,296).

The Tuning_Word is just a 32-bit number. So in this case, for each increment of the tuning word, out frequency of output increases by 57.220mHz (that's milliHertz).

If we rearrange this equation a little to solve for the Tuning_Word, we get this equation:

(2)

So say that we want an output frequency of 15.000MHz. We would compute the tuning word like this:

We then convert this to a 32-bin register value in hexadecimal and that is our tuning word. In this case, expressed as a hexadecimal number we have 0x0FA00000 (The "0x" is a common prefix to indicate we are going to be providing a hexadecimal number). Because our calculation has no remainder (it divides evenly), our output frequency is guaranteed to have the same accuracy of the input frequency (reference). But what if we want to tune to 14.103MHz ? Working the equation again, we get:

If we convert 246,467,788 this to a 32-bit hex tuning word, we have 0x0EB0CCCC ... the "CCCC" on the end is the repeating decimal you see above. We are ignoring, or discarding, the 0.8888 remainder because we can't express it in our 32-bit number because we ran out of places. The other option we have is to get closer to our desired number by rounding up and getting 0x0EB0CCCD. Either way, we are discarding a little bit. So our actual output frequencies using both of these numbers and equation (1) above would be:

Output_Frequency = 246,467,788 * 245760000 / 2^32 = 14.102999.954 MHz

Output_Frequency = 246,467,789 * 245760000 / 2^32 = 14.103000.011 MHz

In the first example, we are 46mHz too low and in the second example we are 11mHz too high.

OK if we assume that you are using a GPS to lock your reference frequency, the GPS will ensure that your reference is perfect, but it will not help with this DDS error that is introduced. In the case of the FLEX-6000, the DDS used is actually an IP block in an FPGA and so there is no "real" output frequency, it is all math, but the math is the same. By now, you can probably see that there are two easy ways to solve this problem:

1. Pick all your tuning frequencies as evenly divisible by your reference frequency (245.76 MHz in this case)

2. Use an arbitrarily large tuning word that ensures that the max error is lower that your tolerance.

Thinking about option 2, if we used a 48-bit DDS tuning word, we would have a maximum error of 873 nHz (nano-Hertz).

So this gives you an idea for where the errors come from and the site of the errors. DDS radios are generally considered significantly better than PLL radios because most people find that a few milliHertz of error in tuning frequency are worth good phase noise. If you are trying to determine a frequency to the nearest micro-Hertz, though, you need some more precision (think ARRL Frequency Measuring Test - FMT).

In the FLEX-6000 series radios if there was just a single DDS, we could easily tell you what the frequency error is. As it turns out, we have many DDSs and it's a little more trouble to calculate the error, but it could be done fairly easily. We have had requests to do this, but as you might imagine we have lots of other things that will affect a larger group of hams that we have been working on first.

I've not watched this, but Analog devices has a webcast to explain the fundamentals of PLLs: http://www.analog.com/en/content/WC_FUN_PLL/webcast.html

In direct digital synthesis (DDS), the frequency is created by actually creating a sine wave over time. Small increments of phase angle are added to an accumulator over time and then the accumulator is examined to create a voltage proportional to the current position of the sine wave. DSS ICs can be purchased and programmed with a microprocessor to perform this function.

I've not watched this one either, but it's from Analog so it's probably very good: Webcast explaining the fundamentals of DDSs:

http://www.analog.com/en/content/WC_FUN_DDS/webcast.html

To create the frequency output, a DDS has a reference clock that serves as its time base. The tuned frequency is loaded into a tuning word. The generalized formula for a DDS to determine the output frequency is:

(1)

*Output_Frequency = Tuning_Word * Sampling_Frequency / Tuning_word_size*(* is a multiply operation, / is a divide operation)

For a 245.76MHz clock (the clock in the FLEX-6700) and a 32-bit tuning word, we get:

*Output_Frequency = Tuning_Word * 245760000 / 2^32*(2^32 is 2 to the 32nd power or 4,294,967,296).

The Tuning_Word is just a 32-bit number. So in this case, for each increment of the tuning word, out frequency of output increases by 57.220mHz (that's milliHertz).

If we rearrange this equation a little to solve for the Tuning_Word, we get this equation:

(2)

*Tuning_Word = Output_Frequency * 2^32 / 245760000*So say that we want an output frequency of 15.000MHz. We would compute the tuning word like this:

*Tuning_Word = 15000000 * 2^32 / 245760000 = 262,144,000*We then convert this to a 32-bin register value in hexadecimal and that is our tuning word. In this case, expressed as a hexadecimal number we have 0x0FA00000 (The "0x" is a common prefix to indicate we are going to be providing a hexadecimal number). Because our calculation has no remainder (it divides evenly), our output frequency is guaranteed to have the same accuracy of the input frequency (reference). But what if we want to tune to 14.103MHz ? Working the equation again, we get:

*Tuning_Word = 14103000 * 2^32 / 245760000 = 246,467,788.88888888888*If we convert 246,467,788 this to a 32-bit hex tuning word, we have 0x0EB0CCCC ... the "CCCC" on the end is the repeating decimal you see above. We are ignoring, or discarding, the 0.8888 remainder because we can't express it in our 32-bit number because we ran out of places. The other option we have is to get closer to our desired number by rounding up and getting 0x0EB0CCCD. Either way, we are discarding a little bit. So our actual output frequencies using both of these numbers and equation (1) above would be:

Output_Frequency = 246,467,788 * 245760000 / 2^32 = 14.102999.954 MHz

Output_Frequency = 246,467,789 * 245760000 / 2^32 = 14.103000.011 MHz

In the first example, we are 46mHz too low and in the second example we are 11mHz too high.

OK if we assume that you are using a GPS to lock your reference frequency, the GPS will ensure that your reference is perfect, but it will not help with this DDS error that is introduced. In the case of the FLEX-6000, the DDS used is actually an IP block in an FPGA and so there is no "real" output frequency, it is all math, but the math is the same. By now, you can probably see that there are two easy ways to solve this problem:

1. Pick all your tuning frequencies as evenly divisible by your reference frequency (245.76 MHz in this case)

2. Use an arbitrarily large tuning word that ensures that the max error is lower that your tolerance.

Thinking about option 2, if we used a 48-bit DDS tuning word, we would have a maximum error of 873 nHz (nano-Hertz).

So this gives you an idea for where the errors come from and the site of the errors. DDS radios are generally considered significantly better than PLL radios because most people find that a few milliHertz of error in tuning frequency are worth good phase noise. If you are trying to determine a frequency to the nearest micro-Hertz, though, you need some more precision (think ARRL Frequency Measuring Test - FMT).

In the FLEX-6000 series radios if there was just a single DDS, we could easily tell you what the frequency error is. As it turns out, we have many DDSs and it's a little more trouble to calculate the error, but it could be done fairly easily. We have had requests to do this, but as you might imagine we have lots of other things that will affect a larger group of hams that we have been working on first.